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Cy620r 433.92 MHz Sop8 Integrated Circuit Wireless RF Receiver Chip IC

Price	$0.30
Min Order	100 Pieces
Availability	In Stock
Shipping From	Guangdong, China
Popularity	365 people viewed

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CY Wireless Technology Limited

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Profile certified by an independent inspection organization.

Guangdong, China
Sonia Sun
Sales Manager

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Product Detail

Model NO.:

CY620R

Conductive Type:

Unipolar Integrated Circuit

Integration:

GSI

Shape:

DIP

Frequency:

433.92 MHz

Sensitivity:

-114dBm

Data Rate:

up to 10kbps

Current:

4.6mA

Voltage:

2.2~5.5V

Ambient Temperature:

-20° C to 70° C

Packaging:

Sop8

Lead Time:

3 Weeks After Receiving Payment

Ship by:

DHL/FedEx/UPS

MOQ:

100PCS

Trademark:

CY

Transport Package:

Reel

Origin:

China

HS Code:

8542399000

Product Description

General Description

The CY620R is a compact, fully integrated OOK/ASK receiver for 433.92 MHz frequency band. It requires few external components. The CY620R consists of a low-noise amplifier (LNA), image-rejection mixer (IRM), built-in channel-select filter (CSF), OOK/ASK demodulator, data filter, and data slicing comparator. The local oscillator (LO) sub-system incorporates a monolithic VCO, ÷32 feedback divider, loop filter and fast start-up reference oscillator to form a complete phase-locked loop-based frequency synthesizer for single channel applications.

The CY620R is available in an 8-pin SOP package and is specified over the temperature range from -20 to +70 °C.

Features

Normal operating of 4.6 mA at 433.92 MHz
Requires few external components
Achieves sensitivity of -114 dBm (peak ASK signal level)
Supply voltage range: 2.2 to 5.5 V
Supports data rates up to 10 Kb/s
Wide input dynamic range with automatic gain control handling
Image-rejection ratio of 25 dB

Applications

Automotive Remote Keyless Entry (RKE)
Remote control
Garage door and gate openers
Suitable for applications that must adhere to either the European ETSI-300-220 or the North American FCC (Part 15) regulatory standards

Pin Configuration

Pin Description

Pin No.	Pin Name	I/O	Description
1	VSS	G	Ground
2	ANT	I	RF input connected to antenna via a matching network
3	VREG	P	Regulated core voltage
4	VDD5	P	5 V regulator input
5	EN	I	Chip enable (tie HIGH to enable the chip)
6	DO	O	Data output
7	CTH	I/O	Connection for data slicing threshold capacitor
8	XIN	I	Reference oscillator input

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